1. Field of the Invention
Generally, the present disclosure relates to the manufacture of FET semiconductor devices, and, more specifically, to various methods of forming PMOS and NMOS FinFET devices on CMOS based integrated circuit products.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided on a restricted chip area. Transistors come in a variety of shapes and forms, e.g., planar transistors, FinFET transistors, nanowire devices, etc. The transistors are typically either NMOS (NFET) or PMOS (PFET) type devices wherein the “N” and “P” designation is based upon the type of dopants used to create the source/drain regions of the devices. So-called CMOS (Complementary Metal Oxide Semiconductor) technology or products refers to integrated circuit products that are manufactured using both NMOS and PMOS transistor devices. Irrespective of the physical configuration of the transistor device, each transistor device comprises laterally spaced apart drain and source regions that are formed in a semiconductor substrate, a gate electrode structure positioned above the substrate and between the source/drain regions, and a gate insulation layer positioned between the gate electrode and the substrate. Upon application of an appropriate control voltage to the gate electrode, a conductive channel region forms between the drain region and the source region and current flows from the source region to the drain region.
A conventional FET is a planar device wherein the entire channel region of the device is formed parallel and slightly below the planar upper surface of the semiconducting substrate. To improve the operating speed of planar FETs, and to increase the density of planar FETs on an integrated circuit product, device designers have greatly reduced the physical size of planar FETs over the past decades. More specifically, the channel length of planar FETs has been significantly decreased, which has resulted in improving the switching speed and in lowering operation currents and voltages of planar FETs. However, decreasing the channel length of a planar FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the planar FET as an active switch is degraded.
In contrast to a planar FET, there are so-called 3D devices, such as an illustrative FinFET device, which is a three-dimensional structure. FIG. 1A is a perspective view of an illustrative prior art FinFET semiconductor device 10 that is formed above a semiconductor substrate 12 wherein the fins 14 of the device 10 are made of the material of the substrate 12, e.g., silicon. The device 10 includes a plurality of trenches 13, three illustrative fins 14, a gate structure 16, a sidewall spacer 18 and a gate cap layer 20. An isolation material 17 provides electrical isolation between the fins 14. The gate structure 16 is typically comprised of a layer of insulating material (not separately shown), e.g., a layer of high-k insulating material, and one or more conductive material layers that serve as the gate electrode for the device 10. The fins 14 have a three dimensional configuration: a height H, a width W and an axial length L. The axial length L corresponds to the direction of current travel in the device 10 when it is operational. The portions of the fins 14 covered by the gate structure 16 are the channel regions of the FinFET device 10. The portions of the fins 14 that are positioned outside of the spacers 18 will become part of the source/drain regions of the device 10.
In the FinFET device 10, the gate structure 16 encloses both sides and the upper surface of the fins 14 to form a tri-gate structure so as to use a channel having a three-dimensional structure instead of a planar structure. In some cases, an insulating cap layer, e.g., silicon nitride, is positioned at the top of the fins 14 and the FinFET device only has a dual-gate structure (sidewalls only). Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to increase the drive current per footprint of the device. Also, in a FinFET, the improved gate control through multiple gates on a narrow, fully-depleted semiconductor fin significantly reduces the short channel effects. When an appropriate voltage is applied to the gate electrode 16 of a FinFET device 10, the surfaces (and the inner portion near the surface) of the fins 14, i.e., the vertically oriented sidewalls and the top upper surface of the fin, form a surface inversion layer or a volume inversion layer that contributes to current conduction. Accordingly, for a given plot space (or foot-print), FinFETs tend to be able to generate significantly higher drive current than planar transistor devices. Additionally, the leakage current of FinFET devices after the device is turned “OFF” is significantly reduced as compared to the leakage current of planar FETs, due to the superior gate electrostatic control of the “fin” channel on FinFET devices. In short, the 3D structure of a FinFET device is a superior MOSFET structure as compared to that of a planar FET, especially in the 20 nm CMOS technology node and beyond.
Device manufacturers are under constant pressure to produce integrated circuit products with increased performance and lower production costs relative to previous device generations. Thus, device designers spend a great amount of time and effort to maximize device performance while seeking ways to reduce manufacturing costs and improve manufacturing reliability. As it relates to 3D devices, device designers have spent many years and employed a variety of techniques in an effort to improve the performance, capability and reliability of such devices. Device designers are currently investigating alternative semiconductor materials, such as SiGe, Ge and III-V materials, to manufacture FinFET devices, which are intended to enhance the performance capabilities of such devices, e.g., to enable low-voltage operation without degrading their operating speed.
FIG. 1B is a perspective view of an illustrative prior art FinFET semiconductor device 10, wherein the overall fin structure of the device includes a substrate fin portion 14A and an alternative fin material portion 14B. As with the case above, the substrate fin portion 14A may be made of silicon, i.e., the same material as the substrate, and the alternative fin material portion 14B may be made of a material other than the substrate material, for example, silicon-germanium, substantially pure germanium, III-V materials, etc. As noted above, the use of such alternative fin materials improves the mobility of charge carriers in the device.
However, the integration of such alternative materials on silicon substrates (the dominant substrates used in the industry) is non-trivial due to, among other issues, the large difference in lattice constants between such alternative materials and silicon. That is, with reference to FIG. 1B, the lattice constant of the alternative fin material portion 14B of the fin 14 may be substantially greater than the lattice constant of the substrate fin portion 14A of the fin 14. As a result of this mismatch in lattice constants, an unacceptable number of defects may be formed or created in the alternative fin material portion 14B. As used herein, a “defect” essentially refers to a misfit dislocation at the interface between the portions 14A and 14B of the fin 14 or threading dislocations that propagate through the portion 14B on the fin 14 at well-defined angles.
With respect to forming such lattice-constant-mismatched materials on one another, there is a concept that is generally referred to as the “critical thickness” of a material. The term “critical thickness” generally refers to materials that are in one of three conditions, i.e., so-called “stable,” “metastable” or “relaxed-with-defects” conditions. These three conditions also generally reflect the state of the strain on the material. That is, a stable material is in a fully-strained condition that is 100% strained in at least one crystalline plane of the material, a relaxed-with-defects material is a material that has zero strain in all crystalline planes, and a metastable material is strained to a level that is above zero strain but less than 100% strained in at least one crystalline plane of the metastable material. In general, a fully-strained (stable) material or a partially-strained (metastable) material will have fewer defects than a fully relaxed, unstrained material.
FIG. 1C is a graph taken from an article entitled “Silicon-Germanium Strained Layer Materials in Microelectronics” by Douglas J. Paul that was published in Advanced Materials magazine (11(3), 101-204 (1999)). FIG. 1C graphically depicts these three conditions for silicon germanium materials (Si1-xGex; x=0-1). The vertical axis is the critical thickness in nanometers. The horizontal axis is the concentration of germanium in the silicon germanium material. At the leftmost point on the horizontal axis is pure silicon (Ge concentration equals 0.0). At the rightmost point on the horizontal axis is pure germanium (Ge concentration equals 1.0). The two curves R and S define the stable, metastable and relaxed-with-defects regions for silicon germanium materials having differing germanium concentration levels. Above and to the right of curve R are materials that are in a relaxed condition with defects present in the material. Below and to the left of the curve S are materials that are in the stable or fully strained condition where there are little or no defects present in the material. The region between the two curves R and S defines the region where materials are in the metastable condition. The graph reflects the critical thickness of various materials when they are grown in an unconfined growth environment, e.g., when growing a substantially planar alternative semiconductor film or layer on the entire upper surface of a silicon substrate.
To add more precision to the terminology regarding critical thickness, the term “stable critical thickness” will be used herein and in the attached claims to refer to a maximum thickness of a material at which it may be formed in a substantially defect-free and “fully-strained” condition above a substrate material in an unconfined growth environment. Additionally, as used herein and in the attached claims, the term “metastable critical thickness” will be used to refer to a maximum thickness of a material at which it may be formed in a metastable condition above a substrate material, i.e., in an unconfined growth environment. As noted above, a material that is in the metastable condition is a material that has experienced some degree of strain-relaxation, but still remains strained to some degree (i.e., 1-99% strained but not 100% strained) in one crystalline plane of the metastable material such that defects are not typically formed in the metastable material itself. However, a metastable material may or may not have some amount of defects at the interface between the alternative material and a silicon substrate depending upon the amount of strain relaxation that has happened to the material.
With reference to FIG. 1C, a layer of pure germanium (Ge concentration equal to 1.0) may be in the stable and fully strained condition at a thickness up to about 1-2 nm (point CT1) and it may be in a metastable condition for thicknesses between about 2-4 nm (point CT2). Above a thickness of about 4 nm, a layer of pure germanium will be in the relaxed-with-defects condition. In contrast, a layer of silicon germanium with a 50% concentration of germanium may be in the stable and fully strained condition at thicknesses up to about 4 nm (point CT3) and it may be in a metastable condition for thicknesses between about 4-30 nm (point CT4). Above a thickness of about 30 nm, a layer of silicon germanium with a 50% concentration of germanium will be in the relaxed-with-defects condition. A material that is in the relaxed-with-defects condition is a material that contains visible defects that are indicative that the material has relaxed to the point where defects have been formed in the material.
As another example, a substantially pure layer of germanium (Ge concentration equal to 1.0) may have a maximum stable critical thickness of about 1-2 nm when formed on a silicon substrate, i.e., in an unconfined growth environment. A substantially pure layer of germanium formed to a thickness of 1-2 nm or less would be considered to be a stable, fully-strained layer of germanium. In contrast, a layer of silicon germanium with a concentration of germanium of about fifty percent (SiGe0.5) may have a maximum stable critical thickness of about 4 nm and still be substantially free of defects, i.e., in a stable condition. However, such a layer of germanium or silicon germanium would no longer be considered to be a stable material if grown beyond their respective maximum stable critical thickness values. When such a layer of material is grown to a thickness that is greater than its maximum stable critical thickness but less than its maximum metastable thickness, it is considered to be a metastable material that would start experiencing some degree of relaxation, i.e., there will be some degree of strain relaxation along one or more of the crystalline planes of the material and there may or may not be some defects present at or near the interface between the alternative fin material and the substrate fin. Thus, in general, the formation of stable, fully-strained, substantially defect-free alternative materials on silicon is limited to very thin layers of the alternative materials.
One of the proposed approaches for the formation of alternative materials for FinFET devices will now be discussed with reference to FIGS. 1D-1H, which are cross-sectional views of the fins taken in a gate width direction of the device 10. As shown in FIG. 1D, the initial fin structures 14 are formed in the substrate 12 by performing an etching process through a patterned etch mask 15. FIG. 1E depicts the device 10 after the layer of insulating material 17 was deposited in the trenches 13 and one or more chemical mechanical polishing (CMP) processes were performed to remove the etch mask 15 and excess amounts of the layer of insulating material 17. These operations expose the upper surface of the fins 14. Next, as shown in FIG. 1F, a timed recessing etching process was performed to remove a portion of the initial fins 14 (now denoted as fins 14A) such that they have a recessed upper surface 14R. Thereafter, as shown in FIG. 1G, the alternative fin material 14B is grown on the recessed fin structures by performing a selective epitaxial deposition process. FIG. 1H depicts the device after a recess etching process was performed on the layer of insulating material 17 such that it has a recessed upper surface 17R that exposes the desired amount of the alternative fin material 14B. At the point of processing depicted in FIG. 1H, traditional manufacturing processes are then performed to form the gate structure 16, gate cap layer 20 and sidewall spacers 18.
Another prior art technique for forming fins made of alternative semiconductor materials involves the formation of one or more so-called SRB (strained relaxed buffer) layers on the silicon substrate (prior to fin-formation) or on the recessed silicon fins prior to formation of the channel semiconductor material, such as a material containing a high concentration of germanium or substantially pure germanium. For example, a germanium channel material formed on an SRB layer having a relatively low percentage of germanium, e.g., 25% or less, can provide substantial band offset isolation for PMOS devices. However, band offset isolation is not possible for an NMOS device using the same SRB layer due to the different nature and composition of an NMOS device and a PMOS device. This is problematic for many integrated circuit products that are manufactured using CMOS technology, i.e., using both NMOS and PMOS devices. The formation of separate SRB layers for NMOS and PMOS devices would increase processing complexity and costs.
It is also known in the prior art to form semiconductor material cladding on the fin of a FinFET device. FIG. 1I is a cross-sectional view of a FinFET 30 device taken through the gate structure 32 in a gate width direction of the device 30. Also depicted are a semiconductor substrate 31, a fin 33, a recessed layer of insulating material 35 and a gate cap layer 39. The gate structure 32 is typically comprised of a layer of gate insulating material 30A, e.g., a layer of high-k insulating material (k-value of 10 or greater) or silicon dioxide, and one or more conductive material layers (e.g., metal, metal alloy, metal stack and/or polysilicon) that serve as the gate electrode 30B for the device 30. In the device 30, the cladding material 34 is the primary current carrying portion of the channel region when the device 30 is operational. Typically, with respect to current day technology, the cladding material 34 may have a thickness of about 2-3 nm. The cladding material 34 is typically an epi semiconductor material, such as silicon germanium, that is formed on the fin 33 by performing known epi deposition processes.
One process flow that is typically performed to form the illustrative FinFET device 30 with the cladding material 34 positioned on the fin 33 is as follows. First, a plurality of trenches 37 were formed in the substrate 31 to define the initial fins 33 (only one fin is shown in FIG. 1I). After the trenches 37 are formed, a layer of insulating material 35, such as silicon dioxide, was formed so as to overfill the trenches 37. Thereafter, a CMP process was performed to planarize the upper surface of the insulating material 35 with the top of the fins 33 (or the top of a patterned hard mask). Thereafter, a recess etching process was performed to recess the layer of insulating material 35 between adjacent fins 33 so as to thereby expose the upper portion of the fin 33. At this point, an epitaxial deposition process was performed to form the cladding material 34 on the exposed portion of the fin 33. Additional steps are then performed to complete the fabrication of the device, i.e., gate formation, sidewall spacer formation, epi material growth in the source/drain regions of the device, etc.
The present disclosure is directed to various methods of forming PMOS and NMOS FinFET devices on CMOS based integrated circuit products that may solve or reduce one or more of the problems identified above.